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U631H256 1 march 31, 2006 stk control #ml0043 rev 1.0 softstore 32k x 8 nvsram the U631H256 has two separate modes of operation: sram mode and nonvolatile mode. in sram mode, the memory operates as an ordinary static ram. in nonvolatile operation, data is transferred in parallel from sram to eeprom or from eeprom to sram. in this mode sram functions are disab- led. the U631H256 is a fast static ram (25 ns), with a nonvolatile electri- cally erasable prom (eeprom) element incorporated in each static memory cell. the sram can be read and written an unlimited num- ber of times, while independent nonvolatile data resides in eeprom. data transfers from the sram to the eeprom (the store operation), or from the eeprom to the sram (the recall operation) are initiated through software sequences. the U631H256 combines the high performance and ease of use of a fast sram with nonvolatile data integrity. once a store cycle is initiated, further input or output are disabled until the cycle is completed. because a sequence of addresses is used for store initiation, it is important that no other read or write accesses intervene in the sequence or the sequence will be aborted. internally, recall is a two step procedure. first, the sram data is cleared and second, the nonvola- tile information is transferred into the sram cells. the recall operation in no way alters the data in the eeprom cells. the nonvolatile data can be recalled an unlimited number of times. the U631H256 is pin compatible with standard srams. pin configuration pin description top view 1 a14 vcc 28 2 a12 w 27 4 a6 a8 25 5 a5 a9 24 3 a7 a13 26 6 a4 a11 23 7 a3 g 22 8 a2 a10 21 12 dq1 dq5 17 9 a1 e 20 10 a0 dq7 19 11 dq0 dq6 18 13 dq2 dq4 16 14 vss dq3 15 sop signal name signal description a0 - a14 address inputs dq0 - dq7 data in/out e chip enable g output enable w write enable vcc power supply voltage vss ground features description high-performance cmos non- volatile static ram 32768 x 8 bits 25 ns access times 10 ns output enable access times software store initiation automatic store timing 10 6 store cycles to eeprom 100 years data retention in eeprom automatic recall on power up software recall initiation unlimited recall cycles from eeprom unlimited read and write to sram single 5 v 10 % operation operating temperature ranges: 0 to 70 c -40 to 85 c qs 9000 quality standard esd protection > 2000 v (mil std 883c m3015.7-hbm) rohs compliance and pb- free package: sop28 (330 mil) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
U631H256 2 march 31, 2006 stk control #ml0043 rev 1.0 operating mode e w g dq0 - dq7 standby/not selected h ** high-z internal read l h h high-z read l h l data outputs low-z write l l * data inputs high-z truth table for sram operations block diagram absolute maximum ratings a symbol min. max. unit power supply voltage v cc -0.5 7 v input voltage v i -0.3 v cc +0.5 v output voltage v o -0.3 v cc +0.5 v power dissipation p d 1w operating temperature c-type k-type t a 0 -40 70 85 c c storage temperature t stg -65 150 c characteristics all voltages are referenced to v ss = 0 v (ground). all characteristics are valid in the power supply volt age range and in the operating temperature range specified. dynamic measurements are based on a rise and fall time of 5 ns, measured between 10 % and 90 % of v i , as well as input levels of v il = 0 v and v ih = 3 v. the timing reference level of all input and output signals is 1.5 v, with the exception of the t dis -times and t en -times, in which cases transition is measured 200 mv from steady-state voltage. * h or l a: stresses greater than those listed under ?a bsolute maximum ratings? may cause permanent damage to the device. this is a stres s rating only, and functional operation of the device at condition above those indicated in the operational sections of this spec ification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. eeprom array 512 x (64 x 8) store recall sram array 512 rows x 64 x 8 columns a5 a6 a7 a8 a9 a11 a12 a13 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 column i/o column decoder store/ recall control row decoder v cc v ss v cc g e w a0 a1 a2 a3 a4 a10 software detect a0 - a13 a14 input buffers
U631H256 3 march 31, 2006 stk control #ml0043 rev 1.0 dc characteristics symbol conditions c-type k-type unit min. max. min. max. operating supply current b i cc1 v cc v il v ih t c = 5.5 v = 0.8 v = 2.2 v = 25 ns 95 100 ma average supply current during store c i cc2 v cc e w v il v ih = 5.5 v v cc -0.2 v v cc -0.2 v 0.2 v v cc -0.2 v 67ma average supply current at t cr = 200 ns b (cycling cmos input levels) i cc3 v cc w v il v ih = 5.5 v v cc -0.2 v 0.2 v v cc -0.2 v 20 20 ma standby supply current d (cycling ttl input levels) i cc(sb)1 v cc e t c = 5.5 v v ih = 25 ns 40 42 ma standby supply curent d (stable cmos input levels) i cc(sb) v cc e v il v ih = 5.5 v v cc -0.2 v 0.2 v v cc -0.2 v 12ma recommended operating conditions symbol conditions min. max. unit power supply voltage v cc 4.5 5.5 v input low voltage v il -2 v at pulse width 10 ns permitted -0.3 0.8 v input high voltage v ih 2.2 v cc +0.3 v b: i cc1 and i cc3 are dependent on output loading and cycle rate. the specified values are obtained with outputs unloaded the current i cc1 is measured for write/read - ratio of 1/2. c: i cc2 is the average current required for the duration of the store cycle (t store ). d: bringing e v ih will not produce standby current levels until any nonvolatile cycle in progress has timed out. the current i cc(sb)1 is measured for write/read - ratio of 1/2.
U631H256 4 march 31, 2006 stk control #ml0043 rev 1.0 dc characteristics symbol conditions min. max. unit output high voltage output low voltage v oh v ol v cc i oh i ol = 4.5 v =-4 ma = 8 ma 2.4 0.4 v v output high current output low current i oh i ol v cc v oh v ol = 4.5 v = 2.4 v = 0.4 v 8 -4 ma ma input leakage current high low i ih i il v cc v ih v il = 5.5 v = 5.5 v = 0 v -1 1 a a output leakage current high at three-state- output low at three-state- output i ohz i olz v cc e or g v oh v ol = 5.5 v v ih = 5.5 v = 0 v -1 1 a a sram memory operation no. switching characteristics read cycle symbol unit alt. iec min. max. 1 read cycle time f t avav t cr 25 ns 2 address access time to data valid g t avqv t a(a) 25 ns 3 chip enable access time to data valid t elqv t a(e) 25 ns 4 output enable access time to data valid t glqv t a(g) 10 ns 5e high to output in high-z h t ehqz t dis(e) 10 ns 6g high to output in high-z h t ghqz t dis(g) 10 ns 7e low to output in low-z t elqx t en(e) 5ns 8g low to output in low-z t glqx t en(g) 0ns 9 output hold time after addr. change g t axqx t v(a) 3ns 10 chip enable to power active e t elicch t pu 0ns 11 chip disable to power standby d, e t ehiccl t pd 25 ns e: parameter guaranteed but not tested. f: device is continuously selected with e and g both low. g: address valid prior to or coincident with e transition low. h: measured 200 mv from steady state output voltage.
U631H256 5 march 31, 2006 stk control #ml0043 rev 1.0 read cycle 1: ai-controlled (during read cycle: e = g = v il , w = v ih ) f no. switching characteristics write cycle symbol unit alt. #1 alt. #2 iec min. max. 12 write cycle time t avav t avav t cw 25 ns 13 write pulse width t wlwh t w(w) 20 ns 14 write pulse width setup time t wleh t su(w) 20 ns 15 address setup time t avwl t avel t su(a) 0ns 16 address valid to end of write t avwh t aveh t su(a-wh) 20 ns 17 chip enable setup time t elwh t su(e) 20 ns 18 chip enable to end of write t eleh t w(e) 20 ns 19 data setup time to end of write t dvwh t dveh t su(d) 10 ns 20 data hold time after end of write t whdx t ehdx t h(d) 0ns 21 address hold after end of write t whax t ehax t h(a) 0ns 22 w low to output in high-z h, i t wlqz t dis(w) 10 ns 23 w high to output in low-z t whqx t en(w) 5ns ai e g dqi t dis(e) t cr t a(e) t en(e) t en(g) t a(g) t dis(g) address valid output data valid i cc active standby t pd t pu (1) (3) (4) (5) (7) (6) (8) (10) (11) t a(a) (2) t a(a) previous data valid output data valid t cr address valid t v(a) (1) (2) (9) read cycle 2: g -, e -controlled (during read cycle: w = v ih ) g ai dqi output output high impedance
U631H256 6 march 31, 2006 stk control #ml0043 rev 1.0 l- to h-level undefined h- to l-level i: if w is low and when e goes low, the outputs remain in the high impedance state. j: e or w must be > v ih during address transitions. write cycle #1: w -controlled j write cycle #2: e -controlled j t h(d) ai e w dqi input dqi output t cw t su(e) t h(a) t w(w) t su(d) t dis(w) t en(w) address valid input data valid high impedance t su(a-wh) (12) (16) (13) (19) (20) (23) (21) t su(a) t h(d) ai e w dqi input dqi output t cw t w(e) t h(a) t su(d) address valid input data valid t su(w) (12) (18) (21) (20) (19) (17) (22) previous data (15) (14) high impedance (15) t su(a) t su(e)
U631H256 7 march 31, 2006 stk control #ml0043 rev 1.0 no. store cycle inhibit and automatic power up recall symbol min. max. unit alt. iec 24 power up recall duration k t restore 650 s low voltage trigger level v switch 4.0 4.5 v nonvolatile memory operations k: t restore starts from the time v cc rises above v switch . store cycle inhibit and automatic power up recall v cc 5.0 v store inhibit power up v switch t restore recall (24) t software mode selection e w a13 - a0 (hex) mode i/o power notes l h 0e38 31c7 03e0 3c1f 303f 0fc0 read sram read sram read sram read sram read sram nonvolatile store output data output data output data output data output data output high z active i cc2 l, m l, m l, m l, m l, m l, m l h 0e38 31c7 03e0 3c1f 303f 0c63 read sram read sram read sram read sram read sram nonvolatile recall output data output data output data output data output data output high z active l, m l, m l, m l, m l, m l, m l: the six consecutive addresses must be in order listed. w must be high during all six consecutive cycles. see store cycle and recall cycle tables and diagrams for further details. the following six-address sequence is used fo r testing purposes and should not be used: 0e38, 31c7, 03e0, 3c1f, 303f, 339c. m: while there are 15 addresses on the U631H256, only th e lower 14 are used to control software modes.
U631H256 8 march 31, 2006 stk control #ml0043 rev 1.0 no. software controlled store/recall cycle l, n symbol unit alt. iec min. max. 25 store/recall initiation time t avav t cr 25 ns 26 chip enable to output inactive o t elqz t dis(e)sr 600 ns 27 store cycle time p t elqxs t d(e)s 10 ms 28 recall cycle time q t elqxr t d(e)r 20 s 29 address setup to chip enable r t aveln t su(a)sr 0ns 30 chip enable pulse width r, s t elehn t w(e)sr 20 ns 31 chip disable to address change r t ehaxn t h(a)sr 0ns n: the software sequence is clocked with e controlled reads o: once the software controlled store or recall cycle is initiated, it completes automatically, ignoring all inputs. p: note that store cycles (but not recall) are aborted by v cc < v switch (store inhibit). q: an automatic recall also takes pl ace at power up, starting when v cc exceeds v switch and takes t restore . v cc must not drop below v switch once it has been exceeded for th e recall to function properly. r: noise on the e pin may trigger multiple read cycles from the same address and abort the address sequence. s: if the chip enable pulse width is less than t a(e) (see read cycle) but greater than or equal t w(e)sr , than the data may not be valid at the end of the low pulse, however the store or recall will still be initiated. software controlled store/recall cycle t, u (e = high after store initiation) addreess 1 address 6 t cr (25) t cr (25) t w(e)sr t h(a)sr (31) t su(a)sr (29) (30) valid high impedance valid t d(e)s (27) (28) t dis(e)sr (26) t d(e)r ai e dqi output software controlled store/recall cycle r, s, t, u (e = low after store initiation) t cr address 1 address 6 (25) t w(e)sr t h(a)sr (31) (30) t su(a)sr (29) t h(a)sr (31) t su(a)sr (29) high impedance valid valid t d(e)s (27) (28) t dis(e)sr (26) t d(e)r t: w must be high when e is low during the address sequence in or der to initiate a nonvolatile cycle. g may be either high or low throughout. addresses 1 through 6 are found in the mode selection table. address 6 determines wheter the U631H256 performs a st ore or recall. u: e must be used to clock in the address sequence for the software controlled store and recall cycles. ai e dqi output
U631H256 9 march 31, 2006 stk control #ml0043 rev 1.0 test configuration for functional check v ih v il v ss v cc w 480 255 30 pf v v o simultaneous measure- ment of all 8 output pins input level according to the relevant test measurement dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 5 v a14 a13 e w g v: in measurement of t dis -times and t en -times the capacitance is 5 pf. w: between v cc and v ss must be connected a high frequency bypass capacitor 0.1 f to avoid disturbances. capacitance e conditions symbol min. max. unit input capacitance v cc v i f t a = 5.0 v = v ss = 1 mhz = 25 c c i 8pf output capacitance c o 7pf all pins not under test must be connected with ground by capacitors. date of manufacture (the first 2 digits indicating the year, and the last 2 digits the calendar week.) leadfree green package product specification internal code operating temperature range c = 0 to 70 c k = -40 to 85 c g1 s 25 c U631H256 type package s2 = sop28 (330mil) type 2 ordering code leadfree option g1 = leadfree green package access time 25 = 25 ns device marking (example) zmd U631H256sc 25 z 0425 g1 example
U631H256 10 march 31, 2006 stk control #ml0043 rev 1.0 device operation the U631H256 has two separate modes of operation: sram mode and nonvolatile mode. the memory ope- rates in sram mode as a standard fast static ram. data is transferred in nonvolatile mode from sram to eeprom shadow (the store operation) or from eeprom to sram (the recall operation). in this mode sram functions are disabled. sram read the U631H256 performs a read cycle whenever e and g are low while w is high. the address speci- fied on pins a0 - a14 determines which of the 32768 data bytes will be accessed. when the read is initia- ted by an address transition, the outputs will be valid after a delay of t cr . if the read is initiated by e or g , the outputs will be valid at t a(e) or at t a(g) , whichever is later. the data outputs will repeatedly respond to address changes within the t cr access time without the need for transition on any control input pins, and will remain valid until another address change or until e or g is brought high or w is brought low. sram write a write cycle is performed whenever e and w are low. the address inputs must be stable prior to entering the write cycle and must remain stable until either e or w goes high at the end of the cycle. the data on pins dq0 - 7 will be written into the memory if it is valid t su(d) before the end of a w controlled write or t su(d) before the end of an e controlled write. it is recommended that g is kept high during the entire write cycle to avoid data bus contention on the common i/o lines. if g is left low, internal circuitry will turn off the output buffers t dis(w) after w goes low. noise consideration the U631H256 is a high speed memory and therefore must have a high frequency bypass capacitor of appro- ximately 0.1 f connected between v cc and v ss using leads and traces that are as short as possible. as with all high speed cmos ics, normal carefull routing of power, ground and signals will help prevent noise pro- blems. software nonvolatile store the U631H256 software controlled store cycle is initiated by executing sequential read cycles from six specific address locations. by relying on read cycles only, the U631H256 implements nonvolatile operation while remaining compatible with standard 32k x 8 srams. during the store cycle, an erase of the pre- vious nonvolatile data is first performed, followed by a program of the nonvolatile elements. once a store cycle is initiated, further inputs and outputs are disabled until the cycle is completed .because a sequence of addresses is used for store initiation, it is important that no other read or write accesses intervene in the sequence or the sequence will be aborted and no store or recall will take place. to initiate the store cycle the following read sequence must be performed: 1. read addresses 0e38 (hex) valid read 2. read addresses 31c7 (hex) valid read 3. read addresses 03e0 (hex) valid read 4. read addresses 3c1f (hex) valid read 5. read addresses 303f (hex) valid read 6. read addresses 0fc0 (hex) initiate store cycle once the sixth address in the sequence has been entered, the store cycle will commence and the chip will be disabled. it is important that read cycles and not write cycles be used in the sequence, although it is not necessary that g be low for the sequence to be valid. after the t store cycle time has been fulfilled, the sram will again be activated for read and write operation. software nonvolatile recall a recall cycle of the eeprom data into the sram is initiated with a sequence of read operations in a manner similar to the store initiation. to initiate the recall cycle the following sequence of read opera- tions must be performed: 1. read addresses 0e38 (hex) valid read 2. read addresses 31c7 (hex) valid read 3. read addresses 03e0 (hex) valid read 4. read addresses 3c1f (hex) valid read 5. read addresses 303f (hex) valid read 6. read addresses 0c63 (hex) initiate recall cycle internally, recall is a two step procedure. first, the sram data is cleared and second, the nonvolatile information is transferred into the sram cells. the recall operation in no way alters the data in the eeprom cells. the nonvolatile data can be recalled an unlimited number of times. automatic power up recall on power up, once v cc exceeds the sense voltage of v switch , a recall cycle is automatically initiated. the voltage on the v cc pin must not drop below
U631H256 11 march 31, 2006 stk control #ml0043 rev 1.0 the information describes the type of component and shall not be considered as assured characteristics. terms of delivery and rights to change design reserved. low average active power the U631H256 has been designed to draw significantly less power when e is low (chip enabled) but the access cycle time is longer than 55 ns. when e is high the chip consumes only standby cur- rent. the overall average current drawn by the part depends on the following items: 1. cmos or ttl input levels 2. the time during which the chip is disabled (e high) 3. the cycle time for accesses (e low) 4. the ratio of reads to writes 5. the operating temperature 6. the v cc level recall; sram operation cannot commence until t restore after v cc exceeds v switch . if the U631H256 is in a write state at the end of power up recall, the sram data will be corrupted. to help avoid this situation, a 10 k resistor should be connected between w and v cc. hardware protection the U631H256 offers hardware protection against inadvertent store operation through v cc sense. for v cc < v switch the software initiated store ope- ration will be inhibited.
simtek corporation 4250 buckingham drive suite 100 ? colorado springs, co 80907 ? usa phone: +(800)637-1667 ? fax: +(719)531-9481 ? email: information@simtek.com ? http://www.simtek.com U631H256 march 31, 2006 life support policy simtek products are not designed, intended, or authorized for use as components in systems intended for sur- gical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the simtek product could create a situation where personal injury or death may occur. components used in life-support devices or systems must be expressly authorized by simtek for such purpose. limited warranty the information in this document has been carefully checked and is believed to be reliable. however simtek corporation (simtek) makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon it. the information in this document describes the type of component and shall not be considered as assured characte- ristics. simtek does not guarantee that the use of any information contained herein will not infringe upon the patent, trademark, copyright, mask work right or other rights of third parties, and no patent or licence is implied hereby. this document does not in any way extent simtek?s warranty on any product beyond that set forth in its stan- dard terms and conditions of sale. simtek reserves terms of delivery and reserves the right to make changes in the products or specifications, or both, presented in this publication at any time and without notice.
change record date/rev name change 01.08.2001 steffen buschbeck changed limit for cmos standby current page 3: i cc(sb) = 2 ma for k-type 01.11.2001 ivonne steffens format revision and release for ?memory cd 2002? 25.09.2002 matthias schniebel adding ?type 1? to sop28 (330 mil) 30.10.2002 matthias schniebel combining U631H256 and U631H256sm in one datasheet 04.12.2003 matthias schniebel operating supply current at t cr = 200 ns: i cc3 = 20 ma 21.04.2004 matthias schniebel adding ?leadfree green package? to ordering information adding ?device marking? 7.4.2005 stefan gnther changing 10 6 endurance cycles and 100a dataretention, mil. temperature range and pdip28 (300mil) deleted, g1 no more on special request, add s2 = sop28 (330mil) type 2 (chip pack) 12.10.2005 stefan gnther change -55c to -40c and m- to a- type in dc characteristics, absolute ratings, ordering code 1.0 simtek assigned simtek document control number

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